Monday, April 30, 2007

LBA-Logical block addressing

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Logical block addressing (LBA) is a common scheme used for specifying the location of blocks of data stored on computer storage devices, generally secondary storage systems such as hard disks. The term LBA can mean either the address or the block to which it refers. Logical blocks in modern computer systems are typically 512 or 1024 bytes each. ISO 9660 CDs (and images of them) use 2048-byte blocks.

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[edit] The LBA scheme

LBA is a particularly simple addressing scheme; blocks are located by an index, with the first block being LBA=0, the second LBA=1, and so on. The LBA scheme replaces earlier schemes which exposed the physical details of the storage device to the software of the operating system. Chief among these was the cylinder-head-sector (CHS) scheme, where blocks were addressed by means of a tuple which defined the cylinder, head, and sector at which they appeared on the hard disk. CHS didn't map well to devices other than hard disks (such as tapes and networked storage), and was generally not used for them. CHS was used in early MFM and RLL drives, and both it and its successor Extended Cylinder-Head-Sector (ECHS) were used in the first ATA drives.

SCSI introduced LBA as an abstraction. While the drive controller still addresses data blocks by their CHS address, this information is generally not used by the SCSI device driver, the OS, filesystem code, or any applications (such as databases) that access the "raw" disk. System calls requiring block-level I/O pass LBA definitions to the storage device driver; for simple cases (where one volume maps to one physical drive), this LBA is then passed directly to the drive controller.

[edit] LBA mapping and LUN virtualization

For more complex cases (particularly RAID devices and SANs and where logical drives (LUNs) are composed via LUN virtualization and aggregation), LBAs are translated from the application's model of the disk to that used by the actual storage device. In complex deployments, particularly when a storage fabric is employed, several of these LBA translations may occur between the dispatching application and the final, remote, disk.

[edit] LBA, ATA devices and Enhanced BIOS

The first formal definition of the ATA interface inherited the CHS scheme from earlier drive standards. This proved to be a limiting factor as ATA drives grew. Originally cylinder, head, and sector were limited to 1024, 16, and 63 respectively. Later, more advanced BIOS implementations (known sometimes as Enhanced BIOS) that virtualised the CHS mapping (often generating many more "virtual" drive heads than the physical disk really possessed) expanded this limit to 1024, 255, and 63. This meant an MS-DOS volume (and a Windows NT 4.0 system partition) was limited to 7.8 GiB.

The second ATA standard (ATA-2) introduced an LBA mode of operation, which has subsequently become the most commonly used scheme when communicating with ATA drives and their technical successors. LBA addresses in ATA can be 28-bit or 48-bit (introduced in ATA-6) wide, which results in a disk size limit of 128 GiB or 128 PiB, respectively, assuming the common 512 bytes per sector.

[edit] External links

注意,磁盘的容量以 10 的幂次来度量,所以 1GB=1,000,000,000 字节,不同于某些其他 PC 值。

APIC-Advanced Programmable Interrupt Controller

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An Advanced Programmable Interrupt Controller (APIC) is a more intricate Programmable Interrupt Controller (PIC) containing a magnitude more outputs and much more complex priority schemas.

One of the best known APIC architectures, the Intel APIC Architecture, is now replacing the original 8259A PIC in newer x86 PCs.

[edit] See also

[edit] External Links

Interrupt request

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In computing, an interrupt request (or IRQ) is a phrase used to refer to either the act of interrupting the bus lines used to signal an interrupt, or the interrupt input lines on a Programmable Interrupt Controller (PIC). Interrupt lines are often identified by an index with the format of IRQ followed by a number. For example, on the Intel 8259 family of PICs there are eight interrupt inputs commonly referred to as IRQ0 through IRQ7. In x86 based computer systems that use two of these PICs, the combined set of lines are referred to as IRQ0 through IRQ15. Technically these lines are named IR0 through IR7, and the lines on the ISA bus to which they were historically attached are named IRQ0 through IRQ15.

Newer x86 systems integrate an APIC that conforms to the Intel APIC Architecture. These APICs support a programming interface for up to 255 physical hardware IRQ lines per APIC, with a typical system implementing support for only around 24 total hardware lines.

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[edit] Overview

When working with computer hardware, installing and removing devices, the system relies on interrupt requests. There are default settings that are configured in the system BIOS and recognized by the operating system. These default settings can be altered by advanced users. Modern Plug and Play technology has not only reduced the need for concern for these settings, but has virtually eliminated manual configuration.

[edit] x86 IRQs

See Intel 8259 for a common list of hardware IRQ lines in x86 systems. The system uses 16 default IRQ's. The easiest way of viewing this information on Windows is to use Device Manager or System Information:

IRQ 0 - System timer. Reserved for the system. Cannot be changed by a user.
IRQ 1 - Keyboard. Reserved for the system. Cannot be altered even if no keyboard is present or needed.
IRQ 2 - Second IRQ controller. See below for explanation.
IRQ 3 - COM 2(Default) COM 4(User)
IRQ 4 - COM 1(Default) COM 3(User)
IRQ 5 - Sound card (Sound Blaster Pro or later) or LPT2(User)
IRQ 6 - Floppy disk controller
IRQ 7 - LPT1(Parallel port) or sound card (8-bit Sound Blaster and compatibles)
IRQ 8 - Real time clock
IRQ 9 - ACPI SCI or ISA MPU-401
IRQ 10 - Free / Open interrupt / Available / SCSI
IRQ 11 - Free / Open interrupt / Available / SCSI
IRQ 12 - PS/2 connector Mouse / If no PS/2 connector mouse is used, this can be used for other peripherals
IRQ 13 - Math co-processor. Cannot be changed
IRQ 14 - Primary IDE. If no Primary IDE this can be changed
IRQ 15 - Secondary IDE

IRQs 0 to 7 are managed by one Intel 8259 PIC, and IRQs 8 to 15 by a second Intel 8259 PIC. The first PIC, the master, is the only one that directly signals the CPU. The second PIC, the slave, instead signals to the master on its IR2 line, and the master passes the signal on. There are therefore only 15 interrupt request lines available for hardware.


[edit] See also

[edit] References

  • Gilluwe, Frank van. The Undocumented PC, Second Edition, Addison-Wesley Developers Press, 1997. ISBN 0-201-47950-8
  • Shanley, Tom. ISA System Architecture, Third Edition, Addison-Wesley Publishing Company, 1995. ISBN 0-201-40996-8
  • Solari, Edward. PCI & PCI-X Hardware and Software Architecture & Design, Sixth Edition, Research Tech Inc., 2004. ISBN 0-9760865-0-6

警告:隐式声明与内建函数 ‘exit’ 不兼容

问:
我在fc5.0下运行parseconfig.c,出现了如下的错误,应该如何解决阿,请高手赐教!是不是这个警告对结果并无影响?

(cd Util; if [ "" != "" ] ; then make -i -r CC="" CFLAGS= ; else make -i -r ; fi )
make[1]: Entering directory `/home/mm5/MM5/Util'
cc -O -o ../parseconfig ./parseconfig.c
./parseconfig.c: 在函数 ‘main’ 中:
./parseconfig.c:139: 警告:隐式声明与内建函数 ‘exit’ 不兼容
./parseconfig.c:204: 警告:隐式声明与内建函数 ‘exit’ 不兼容
./parseconfig.c:305: 警告:隐式声明与内建函数 ‘exit’ 不兼容
./parseconfig.c:384: 警告:隐式声明与内建函数 ‘exit’ 不兼容
./parseconfig.c:460: 警告:隐式声明与内建函数 ‘exit’ 不兼容
./parseconfig.c:469: 警告:隐式声明与内建函数 ‘exit’ 不兼容
./parseconfig.c:477: 警告:隐式声明与内建函数 ‘exit’ 不兼容
make[1]: Leaving directory `/home/mm5/MM5/Util'
./parseconfig; \

答:
在那个c文件头里加上
#include

P.S: 下一次遇到这种情况,export LANG=en_US,然后再次运行,将警告或者错误信息贴到google里搜一下,应该可以找到答案